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19-0279; Rev 0; 8/94
5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC
_______________General Description
The MAX503 is a low-power, 10-bit, voltage-output digitalto-analog converter (DAC) that uses single 5V or dual 5V supplies. This device has an internal voltage reference plus an output buffer amplifier. Operating current is only 250A from a single 5V supply, making it ideal for portable and battery-powered applications. In addition, the shrink smalloutline package (SSOP) measures only 0.1 square inches, using less board area than an 8-pin DIP. 10-bit resolution is achieved through laser trimming of the DAC, op amp, and reference. No further adjustments are necessary. Internal gain-setting resistors can be used to define a DAC output voltage range of 0V to +2.048V, 0V to +4.096V, or 2.048V. Four-quadrant multiplication is possible without the use of external resistors or op amps. The parallel logic inputs are double buffered and are compatible with 4-bit, 8bit, and 16-bit microprocessors. For a hardware and software compatible 12-bit upgrade, refer to the MAX530 data sheet. For DACs with similar features but with a serial data interface, refer to the MAX504/MAX515 data sheet.
____________________________Features
o o o o o o o o o o Buffered Voltage Output Internal 2.048V Voltage Reference Operates from Single 5V or Dual 5V Supplies Low Power Consumption: 250A Operating Current 40A Shutdown-Mode Current SSOP Package Saves Space Relative Accuracy: 1/2 LSB Max Over Temperature Guaranteed Monotonic Over Temperature 4-Quadrant Multiplication with No External Components Power-On Reset Double-Buffered Parallel Logic Inputs
MAX503
______________Ordering Information
PART MAX503CNG MAX503CWG MAX503CAG MAX503ENG MAX503EWG MAX503EAG TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 24 Narrow Plastic DIP 24 Wide SO 24 SSOP 24 Narrow Plastic DIP 24 Wide SO 24 SSOP
________________________Applications
Battery-Powered Data-Conversion Products Minimum Component-Count Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Arbitrary Function Generators Automatic Test Equipment Microprocessor-Controlled Calibration
Refer to the MAX530 for military temperature or die equivalents.
________________Functional Diagram
REFOUT 18 2.048V REFERENCE 17 REFGND 14 AGND POWER-ON RESET 15 CLR 8 A0 9 A1 11 CS WR 10 16 LDAC 20 DAC 23 VDD DGND VSS VOUT REFIN ROFS 13 22 21 RFB
__________________Pin Configuration
TOP VIEW
D7/S1 1 D8/D0 2 D9/D1 3 D2 4 D3 5 D4 6 D5 7 A0 8 24 D6/S0 23 VDD 22 ROFS 21 RFB
MAX503
20 VOUT 19 VSS 18 REFOUT 17 REFGND 16 LDAC 15 CLR 14 AGND 13 REFIN
MAX503
10-BIT DAC LATCH DAC LATCH
12 19
CONTROL LOGIC
NBL INPUT LATCH
NBM INPUT LATCH
NBH INPUT LATCH
A1 9 WR 10 CS 11 DGND 12 DIP/SO/SSOP
24 1 2 3 4 5 6 7 D2 D4 D6/S0 D8/D0 D7/S1 D9/D1 D3 D5
________________________________________________________________ Maxim Integrated Products
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
ABSOLUTE MAXIMUM RATINGS
VDD to DGND and VDD to AGND ................................-0.3V, +6V VSS to DGND and VSS to AGND .................................-6V, +0.3V VDD to VSS ............................................................... -0.3V, +12V AGND to DGND........................................................-0.3V, +0.3V REFGND to AGND.........................................-0.3V, (VDD + 0.3V) Digital Input Voltage to DGND .................... -0.3V, (VDD + 0.3V) REFIN ..................................................(VSS - 0.3V), (VDD + 0.3V) REFOUT ..............................................(VSS - 0.3V), (VDD + 0.3V) REFOUT to REFGND .................................... -0.3V, (VDD + 0.3V) RFB ....................................................(VSS - 0.3V), (VDD + 0.3V) ROFS ..................................................(VSS - 0.3V), (VDD + 0.3V) VOUT to AGND (Note 1) .............................................. VSS, VDD Continuous Current, Any Input ........................................20mA Continuous Power Dissipation (TA = +70C) Narrow Plastic DIP (derate 13.33mW/C above +70C) ...1067mW Wide SO (derate 11.76mW/C above +70C)............... 941mW SSOP (derate 8.00mW/C above +70C) ......................640mW Operating Temperature Ranges MAX503C_G .........................................................0C to +70C MAX503E_G ......................................................-40C to +85C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10sec) ........................... +300C
Note 1: The output may be shorted to VDD, VSS, DGND, or AGND if the continuous package power dissipation and current ratings are not exceeded. Typical short-circuit currents are 20mA.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--Single +5V Supply
(VDD = 5V, VSS = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33F, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Unipolar Offset Error Unipolar Offset Temperature Coefficient Unipolar Offset-Error Supply Rejection Gain Error (Note 2) Gain-Error Temperature Coefficient Gain-Error Power-Supply Rejection DAC VOLTAGE OUTPUT (VOUT) Output Voltage Range Resistive Load DC Output Impedance Short-Circuit Current REFERENCE INPUT (REFIN) Reference Input Range Reference Input Resistance Reference Input Capacitance AC Feedthrough Code dependent, minimum at code 0101... Code dependent (Note 3) (Note 4) 0 40 10 -80 50 VDD - 2 V k pF dB ISC VOUT = 2V, load regulation 0.5LSB 0 2 0.2 12 VDD - 0.4 V k mA PSRR 4.5V VDD 5.5V N INL DNL VOS TCVOS PSRR GE 4.5V VDD 5.5V DAC latch = all 1s, VOUT < VDD - 0.4V (Note 2) 1 0.1 (Note 2) Guaranteed monotonic 0 0.25 3 0.1 1 10 0.5 1 3 Bits LSB LSB LSB ppm/C LSB/V LSB ppm/C LSB/V SYMBOL CONDITIONS MIN TYP MAX UNITS
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
ELECTRICAL CHARACTERISTICS--Single +5V Supply (continued)
(VDD = 5V, VSS = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33F, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL TA = +25C Reference Tolerance Reference Output Resistance Power-Supply Rejection Ratio Noise Voltage Temperature Coefficient Required External Capacitor DYNAMIC PERFORMANCE Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Signal-to-Noise Plus Distortion Ratio Logic High Input Logic Low Input Digital Leakage Current Digital Input Capacitance POWER SUPPLIES Positive Supply-Voltage Range Positive Supply Current SWITCHING CHARACTERISTICS Address to WR Setup Address to WR Hold CS to WR Setup CS to WR Hold Data to WR Setup Data to WR Hold WR Pulse Width LDAC Pulse Width CLR Pulse Width Internal Power-On Reset Pulse Width tAWS tAWH tCWS tCWH tDS tDH tWR tLDAC tCLR tPOR (Note 3) 5 5 0 0 45 0 45 45 45 1.3 10 ns ns ns ns ns ns ns ns ns s VDD IDD Outputs unloaded, all digital inputs = 0V or VDD 4.5 250 5.5 400 V A SINAD TA = +25C To 0.5LSB, VOUT = 2V WR = VDD, digital inputs all 1s to all 0s Unity gain (Note 4) Gain = 2 (Note 4) 2.4 0.8 VIN = 0V or VDD 8 1 0.15 0.25 25 5 68 68 V/s s nV-s dB CREFOUT 3.3 VREFOUT RREFOUT PSRR en MAX503C MAX503E (Note 5) 4.5V VDD 5.5V 0.1Hz to 10kHz 200 400 30 CONDITIONS MIN 2.024 2.015 2.011 TYP 2.048 MAX 2.072 2.081 2.085 2 V/V Vp-p ppm/C F V UNITS
REFERENCE OUTPUT (REFOUT)
DIGITAL INPUTS (S0, S1, D0-D9, LDAC, CLR, CS, WR, A0, A1) VIH VIL V V A pF
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
ELECTRICAL CHARACTERISTICS--Dual 5V Supplies
(VDD = 5V, VSS = -5V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33F, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Bipolar Offset Error Bipolar Offset Temperature Coefficient Bipolar Offset-Error Power-Supply Rejection Gain Error
Gain-Error Temperature Coefficient Gain-Error Power-Supply Rejection
SYMBOL N INL DNL VOS TCVOS PSRR
CONDITIONS
MIN 10
TYP
MAX
UNITS Bits
+0.5 Guaranteed monotonic 1 3 3 4.5V VDD 5.5V, -5.5V VSS -4.5V 0.1 1
LSB LSB LSB ppm/C LSB/V LSB ppm/C LSB/V
TC PSRR 4.5V VDD 5.5V, -5.5V VSS -4.5V VSS + 0.4 VOUT = 2V, load regulation 0.5LSB ISC VSS + 2 Code dependent, minimum at code 0101... Code dependent (Note 3) (Note 4) 40 10 2
1 0.1 VDD - 0.4 0.2 20 VDD - 2 50 -80
DAC VOLTAGE OUTPUT (VOUT) Output Voltage Range Resistive Load DC Output Impedance Short-Circuit Current REFERENCE INPUT (REFIN) Reference Input Range Reference Input Resistance Reference Input Capacitance AC Feedthrough V k pF dB V k mA
REFERENCE OUTPUT (REFOUT)--Specifications are identical to those under Single +5V Supply DYNAMIC PERFORMANCE--Specifications are identical to those under Single +5V Supply DIGITAL INPUTS (S0, S1, D0-D9, LDAC, CLR, CS, WR, A0, A1)--Specifications are identical to those under Single +5V Supply POWER SUPPLIES Positive Supply Voltage Negative Supply Voltage Positive Supply Current VDD VSS IDD Outputs unloaded, all digital inputs = 0V or VDD 4.5 -5.5 250 150 5.5 0 400 200 V V A A
Negative Supply Current ISS Outputs unloaded, all digital inputs = 0V or VDD SWITCHING CHARACTERISTICS--Specifications are identical to those under Single +5V Supply Note 2: Note 3: Note 4: Note 5:
In single supply, INL and GE are calculated from code 3 to code 1023 (code excludes S0 and S1). Guaranteed by design. REFIN = 1kHz, 2.0Vp-p. Tested at IOUT = 100A. The reference can typically source up to 5mA (see Typical Operating Characteristics).
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC
__________________________________________Typical Operating Characteristics
(Single +5V supply, unity gain, code = all 1s, TA = +25C, unless otherwise noted.)
OUTPUT SINK CAPABILITY vs. OUTPUT PULL-DOWN VOLTAGE
MAX503-1
MAX503
OUTPUT SOURCE CAPABILITY vs. OUTPUT PULL-UP VOLTAGE
MAX503-2
ANALOG FEEDTHROUGH vs. FREQUENCY
-100 ANALOG FEEDTHROUGH (dB) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 CODE = ALL 0s, DUAL SUPPLIES (5V) 1 10 100 1k 10k 100k 1M REFIN = 2Vp-p
MAX503-3
16 OUTPUT SINK CAPABILITY (mA) 14 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8
8 OUTPUT SOURCE CAPABILITY (mA) 7 6 5 4 3 2 1 0
-110
1.0
0
1
2
3
4
5
OUTPUT PULL-DOWN VOLTAGE (V)
OUTPUT PULL-UP VOLTAGE (V)
FREQUENCY (Hz)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX503-4
SUPPLY CURRENT vs. TEMPERATURE
MAX503-5
GAIN vs. FREQUENCY
2 0 -2 GAIN (dB) REFIN = 4Vp-p
MAX503-6
2.055
300 290 SUPPLY CURRENT (A) 280 270 260 250 240
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REFERENCE VOLTAGE (V)
-4 -6 -8 -10 -12 -14 DUAL SUPPLIES (5V)
2.050
2.045 -60 -40 -20 40 60 80 100 120 140 TEMPERATURE (C) 0 20
230 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
1
100
1k FREQUENCY (Hz)
10k
100k
AMPLIFIER SIGNAL-TO- NOISE RATIO
MAX503-7
GAIN AND PHASE vs. FREQUENCY
(G = 2) (G = 1) 100 GAIN
MAX503-8
80 REFIN = 4Vp-p SIGNAL-TO-NOISE RATIO (dB) 70 60
200
180
GAIN (dB)
50 40 30 DUAL SUPPLIES (5V) 20 10 0 10 100 1k FREQUENCY (Hz) 10k 100k
0 PHASE -100 0
-200
-300 1 10 100 800 FREQUENCY (kHz)
-180
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PHASE SHIFT (Degrees)
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
____________________________Typical Operating Characteristics (continued)
(Single +5V supply, unity gain, code = all 1s, TA = +25C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE vs. REFERENCE LOAD CURRENT
MAX503-10 MAX503-9
SUPPLY CURRENT vs. REFIN
250 REFGND = AGND 200 SUPPLY CURRENT (A) 2.0480 2.0475 REFERENCE OUTPUT (V) 2.0470 2.0465 2.0460 2.0455 EXTERNAL REFERENCE 0 0 50 100 150 200 250 300 350 400 450 500 REFIN (mV) 2.0450 0
150
100
REFGND = VDD
50
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE LOAD CURRENT (mA)
DIGITAL FEEDTHROUGH
A
B
2s/div A: S0, S1, D0-D9 = 100kHz, 4Vp-p B: VOUT, 10mV/div LDAC = CS = HIGH
SETTLING TIME (FALLING)
SETTLING TIME (RISING)
A A B
B
5s/div
A: DIGITAL INPUTS FALLING EDGE, 5V/div B: VOUT, NO LOAD, 1V/div DUAL SUPPLY (5V) LDAC = LOW BIPOLAR CONFIGURATION VREFIN = 2V
5s/div
A: DIGITAL INPUTS RISING EDGE, B: VOUT, NO LOAD, 1V/div DUAL SUPPLY (5V) LDAC = LOW BIPOLAR CONFIGURATION VREFIN = 2V
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 NAME D7/ S1 D8/ D0 D9/ D1 D2 D3 D4 D5 A0 FUNCTION D7 input when A0 = A1 = 1, or S1 input when A0 = 0 and A1 = 1. Always set S1 to 0.* D8 input when A0 = A1 = 1, or D0 input when A0 = 0 and A1 = 1.* D9 input when A0 = A1 = 1, or D1 input when A0 = 0 and A1 = 1.* D2 Input Data, or tie to S0 and multiplex when A0 = 1 and A1 = 0.* D3 Input Data, or tie to S1 and multiplex when A0 = 1 and A1 = 0.* D4 Input Data, or tie to D0 and multiplex when A0 = 1 and A1 = 0.* D5 Input Data, or tie to D1 and multiplex when A0 = 1 and A1 = 0.* Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM), and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.) Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and A1 = 0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing. Write Input (active low). Used with CS to load data into the input latch selected by A0 and A1. Chip Select (active low). Enables addressing and writing to this chip from common bus lines. Digital Ground Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to REFOUT (pin 18) to use the internal 2.048V reference. Analog Ground Clear (active low). A low on CLR resets the DAC latches to all 0s. Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input latch to the DAC latch and updates VOUT. Reference Ground must be connected to AGND when using the internal reference. Connect to VDD to disable the internal reference and save power. Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC. Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation. Voltage Output. Op-amp buffered DAC output. Feedback Pin. Op-amp feedback resistor. Always connect to VOUT. Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output. Positive Power Supply (+5V) D6 input when A0 = A1 = 1, or S0 input when A0 = 0 and A1 = 1. Always set S0 to 0.*
MAX503
9 10 11 12 13 14 15 16
A1 WR CS DGND REFIN AGND CLR LDAC
17 18 19 20 21 22 23 24
REFGND REFOUT VSS VOUT RFB ROFS VDD D6/S0
* This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode. _______________________________________________________________________________________ 7
5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
________________Detailed Description
The MAX503 consists of a parallel-input logic interface, a 10-bit R-2R ladder, a reference, and an op amp. The Functional Diagram shows the control lines and signal flow through the input data latch to the DAC latch, as well as the 2.048V reference and output op amp. Total supply current is typically 250A with a single +5V supply. This circuit is ideal for battery-powered, microprocessor-controlled applications where high accuracy, no adjustments, and minimum component count are key requirements. the reference voltage. The MAX503's topology makes the ladder output voltage the same polarity as the reference input, making the device suitable for single-supply operation. The BiCMOS op amp is then used to buffer, invert, or amplify the ladder signal. Ladder resistors are nominally 80k to conserve power and are laser trimmed for gain and linearity. The input impedance at REFIN is code dependent. When the DAC register is all 0s, all rungs of the ladder are grounded and REFIN is open or no load. Maximum loading (minimum REFIN impedance) occurs at code 010101.... Minimum reference input impedance at this code is guaranteed to be not less than 40k. The REFIN and REFOUT pins allow the user to choose between driving the R-2R ladder with the on-chip reference or an external reference. REFIN may be below analog ground when using dual supplies. See the External Reference and Four-Quadrant Multiplication sections for more information.
R-2R Ladder
The MAX503 uses an "inverted" R-2R ladder network with a BiCMOS op amp to convert 10-bit digital data to analog voltage levels. Figure 1 shows a simplified diagram of the R-2R DAC and op amp. Unlike a standard DAC, the MAX503 uses an "inverted" ladder network. Normally, the REFIN pin is the current output of a standard DAC and would be connected to the summing junction, or virtual ground, of an op amp. In this standard DAC configuration, however, the output voltage would be the inverse of
Internal Reference
The on-chip reference is laser trimmed to generate 2.048V at REFOUT. The output stage can source and sink current so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically, source current is 5mA and sink current is 100A. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladder draws 50A maximum load current. If any other connection is made to REFOUT, ensure that the total load current is less than 100A to avoid gain errors. A separate REFGND pin is provided to isolate reference currents from other analog and digital ground currents. To achieve specified noise performance, connect a 33F capacitor from REFOUT to REFGND (see Figure 2). Using smaller capacitance values increases noise, and values less than 3.3F may compromise the reference's stability. For applications requiring the lowest noise, insert a buffered RC filter between REFOUT and REFIN. When using the internal reference, REFGND must be connected to AGND. In applications not requiring the internal reference, connect REFGND to VDD, which shuts down the reference. This saves typically 100A of VDD supply current and eliminates the need for CREFOUT.
2R
MAX503
R 2R 2R LSB 2R R 2R R 2R
2R
ROFS RFB
VOUT OUTPUT BUFFER
*
REFIN AGND REFOUT 2.048V REFGND
MSB R = 80k
LSB
DAC LATCH
MSB
CLR
NBL INPUT LATCH
NBM INPUT LATCH
NBH INPUT LATCH
D2 D4 D6/S0 D8/D0 D7/S1 D3 D5 D9/D1
*SHOWN FOR ALL 1s
Figure 1. Simplified MAX503 DAC Circuit
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC
External Reference
REFOUT CREFOUT
TEK 7A22
MAX503
RS CS TOTAL REFERENCE NOISE
SINGLE POLE ROLLOFF REFERENCE NOISE (VRMS) 250 CREFOUT = 3.3F 200 150 100 50 0 0.1 1 10 FREQUENCY (kHz) 100 CREFOUT = 47F
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1000
MAX503-FIG02
300
1.8
REFERENCE NOISE (mVp-p)
An external reference in the range (V SS + 2V) to (VDD - 2V) may be used with the MAX503 in dual-supply, unity-gain operation. In single-supply, unity-gain operation, the reference must be positive and may not exceed (VDD - 2V). The reference voltage determines the DAC's full-scale output. If an upgrade to the internal reference is required, the 2.5V MAX873A is ideal: 15mV initial accuracy, 7ppm/C (max) temperature coefficient.
Power-On Reset
An internal power-on reset (POR) circuit forces the DAC register to reset to all 0s when VDD is first applied. The POR pulse is typically 1.3s; however, it may take 2ms for the internal reference to charge its large filter capacitor and settle to its trimmed value. In addition to POR, a clear (CLR) pin, when held low, sets the DAC register to all 0s. CLR operates asynchronously and independently from chip select (CS). With the DAC input at all 0s, the op-amp output is at zero for unity-gain and G = 2 configurations, but it is at -VREF for the bipolar configuration.
Figure 2. Reference Noise vs. Frequency
Output Buffer
The output amplifier uses a folded cascode input stage and a type AB output stage. Large output devices with low series resistance allow the output to swing to ground in single-supply operation. The output buffer is unity-gain stable. Input offset voltage and supply current are laser trimmed. Settling time is 25s to 0.01% of final value. The output is short-circuit protected and can drive a 2k load with more than 100pF of load capacitance. The op amp may be placed in unity-gain (G = 1), in a gain of two (G = 2), or in a bipolar-output mode by using the ROFS and RFB pins. These pins are used to define a DAC output voltage range of 0V to +2.048V, 0V to +4.096V or 2.048V, by connecting ROFS to VOUT, GND, or REFIN. RFB is always connected to VOUT. Table 1 summarizes ROFS usage.
Shutdown Mode
The MAX503 is designed for low power consumption. Understanding the circuit allows power consumption management for maximum efficiency. In single-supply mode (VDD = +5V, VSS = GND) the initial supply current is typically only 160A, including the reference, op amp, and DAC. This low current occurs when the power-on reset circuit clears the DAC to all 0s and forces the op-amp output to zero (unipolar mode only). See the Supply Current vs. REFIN graph in the Typical Operating Characteristics. Under this condition, there is no internal load on the reference (DAC = all 0s, REFIN is open circuit) and the op amp operates at its minimum quiescent current. The CLR signal resets the MAX503 to these same conditions and can be used to control a power-saving mode when the DAC is not being used by the system.
Table 1. ROFS Usage
ROFS CONNECTED TO: VOUT AGND REFIN DAC OUTPUT RANGE 0V to 2.048V 0V to 4.096V -2.048V to +2.048V OP-AMP GAIN G=1 G=2 Bipolar
Note: Assumes RFB = VOUT and REFIN = REFOUT = 2.048V
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
REFOUT
REFIN
ROFS
33F 2.048V REFERENCE REFGND 2N7002 AGND DGND POWER-ON RESET DAC VOUT RFB
MAX503
VDD 10-BIT DAC LATCH +5V
CLR
CLR VSS A0 A1 CS WR LDAC CONTROL LOGIC NBL INPUT LATCH NBM INPUT LATCH NBH INPUT LATCH
D2 D4 D6/S0 D8/D0 D7/S1 D3 D5 D9/D1
Figure 3. Low-Current Shutdown Mode
Table 2. Input Latch Addressing
CLR CS WR LDAC
L H H H H H H H H 10 X H X L L L H L L X X H L L L H L L X H H H H H L X L A0 X X X H H L X L H A1 X X X H L H X L H DATA UPDATED Reset DAC latches No operation No operation NBH (D6-D9) NBM (D2-D5) NBL (S0 = 0, S1 = 0, D0, D1) Update DAC only NBL and NBM (S0, S1, D0-D5), DAC not updated NBH and update DAC
An additional 110A of supply current can be saved when the internal reference is not used by connecting REFGND to VDD. A low on-resistance N-channel FET, such as the 2N7002, can be used to turn off the internal reference to create a shutdown mode with minimum current drain (Figure 3). When CLR is high, the transistor pulls REFGND to AGND and the reference and DAC operate normally. When CLR goes low, REFGND is pulled up to VDD and the reference is shut down. At the same time, CLR resets the DAC register to all 0s, and the op-amp output goes to 0V for unity-gain and G = 2 modes. This reduces the total single-supply operating current from 250A (400A max) to typically 40A in shutdown mode.
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
ADDRESS BUS VALID A0-A1 VIH VIL tAWH CS
tCWS WR tAWS tWR
tCWH
tDS DATA BITS (8-BIT BYTE OR 4-BIT NIBBLE) CLR tCLR VIH VIL
DATA BUS VALID
tDH
LDAC NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL 2
tLDAC
Figure 4. MAX503 Write-Cycle Timing Diagram
A small error voltage is added to the reference output by the reference current flowing through the N-channel pull-down transistor. The switch's on resistance should be less than 5. A typical reference current of 100A would add 0.5mV to REFOUT. Since the reference current and on resistance increase with temperature, the overall temperature coefficient will degrade slightly. As data is loaded into the DAC and the output moves above GND, the op-amp quiescent current increases to its nominal value and the total operating current averages 250A. Using dual supplies (5V), the op amp is fully biased continuously, and the VDD supply current is more constant at 250A. The VSS current is typically 150A. The MAX503 logic inputs are compatible with TTL and CMOS logic levels. However, to achieve the lowest power dissipation, drive the digital inputs with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approximately 2.
Parallel Logic Interface
In order to provide hardware and software compatibility with the 12-bit MAX530, the MAX503 employs a 12-bit digital interface. As shown in Figure 3, there is actually a 12-bit input latch, and therefore 12 bits of data should be written. The two least significant bits (S1 and S0) are sub-LSB, and must always be 0s. Designed to interface with 4-bit, 8-bit, and 16-bit microprocessors (Ps), the MAX503 uses 8 data pins and double-buffered logic inputs to load data as 4 + 4 + 4 or 8 + 4. The 12-bit DAC latch is updated simultaneously through the control signal LDAC. Signals A0, A1, WR, and CS select which input latches to update. The 12-bit data is broken down into nibbles (NB); NBL is the enable signal for the lowest 4 bits (S0, S1, D0, D1), NBM is the enable for the middle 4 bits, and NBH is the enable for the highest and most significant 4 bits. Table 2 lists the address decoding scheme. Refer to Figure 4 for the MAX503 write-cycle timing diagram.
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11
5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
D0-D3 DATA BUS D0-D3 D0-D3 D0-D7 DATA BUS D0-D7
FROM SYSTEM RESET MC6800 2 R/W
S0, S1, D0, D1 CLR A0, A1 WR
D2-D5
FROM SYSTEM RESET MC6809 E
CLR
S0, S1, D0-D5
MAX503
CS LDAC
A0-A1 WR
MAX503
CS LDAC
EN
DECODER
R/W
EN
DECODER
A0-A15
ADDRESS BUS
A0, A1
A13-A15
A0-A15 ADDRESS BUS A0
A13-A15
Figure 5. 4-Bit P Interface
Figure 7. 8-Bit and 16-Bit P Interface
NBH NBM NBL CS WR LDAC
A0 = 1, A1 = 1 A0 = 1, A1 = 0 A0 = 0, A1 = 1
DAC UPDATE
Figure 6. 4-Bit P Timing Sequence
NBH NBL & NBM CS WR LDAC
A0 = A1 = 1 A0 = A1 = 0
DAC UPDATE
Figure 8a. 8-Bit and 16-Bit P Timing Sequence Using LDAC
12 ______________________________________________________________________________________
5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
NBL & NBM NBH CS WR A0 = A1 = 0 A0 = A1 = 1
LDAC = 0 (DAC LATCH IS TRANSPARENT) DAC UPDATE
Figure 8b. 8-Bit and 16-Bit P Timing Sequence with LDAC = 0
+5V +5V
REFIN REFOUT 33F AGND DGND REFGND
VDD ROFS 33F
REFIN REFOUT
VDD
MAX503
RFB
ROFS AGND
MAX503
RFB VOUT
VOUT
VOUT
DGND REFGND
VOUT
VSS 0V TO -5V
G=1
VSS 0V TO -5V
G=2
Figure 9. Unipolar Configuration (0V to +2.048V Output)
Figure 10. Unipolar Configuration (0V to +4.096V Output)
Figure 5 shows the circuit configuration for a 4-bit P application. Figure 6 shows the corresponding timing sequence. The 4 low bits (S0, S1, D0, D1) are connected in parallel to the other 4 bits (D2-D5) and then to the P bus. Address lines A0 and A1 enable the input data latches for the high, middle, or low data nibbles. The P sends chip select (CS) and write (WR) signals to latch in each of three nibbles in three cycles when the data is valid. Figure 7 shows a typical interface to an 8-bit or a 16-bit P. Connect 8 data bits from the data bus to pins S0, S1, and D0-D5 on the MAX503. With LDAC held high, the user can load NBH or NBL + NBM in any order. Figure 8a shows the corresponding timing sequence. For fastest throughput, use Figure 8b's sequence. Address lines A0 and A1 are tied together and the DAC is loaded in 2 cycles as 8 + 4. In this scheme, with LDAC held low, the DAC latch is transparent. Always load NBL and NBM first, followed by NBH.
LDAC is asynchronous with respect to WR. If LDAC is brought low before or at the same time WR goes high, LDAC must remain low for at least 50ns to ensure the correct data is latched. Data is latched into DAC registers on LDAC's rising edge.
Unipolar Configuration
The MAX503 is configured for a 0V to VREFIN unipolar output range by connecting ROFS and RFB to VOUT (Figure 9). The converter operates from either single or dual supplies in this configuration. See Table 3 for the DAC-latch contents (input) vs. the analog VOUT (output). In this range, 1LSB = VREFIN (2 -10). A 0V to 2VREFIN unipolar output range is set up by connecting ROFS to AGND and RFB to VOUT (Figure 10). Table 4 shows the DAC-latch contents vs. VOUT. The MAX503 operates from either single or dual supplies in this mode. In this range, 1LSB = (2)(VREFIN)(2 -10) = (VREFIN)(2 -9).
13
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
Table 3. Unipolar Binary Code Table (0V to VREFIN Output), Gain = 1
INPUT* 1111 1111 11(00) OUTPUT (VREFIN) 1023 1024 513 1024
Table 4. Unipolar Binary Code Table (0V to 2VREFIN Output), Gain = 2
INPUT* 1111 1111 11(00) OUTPUT +2 (VREFIN) 1023 1024 513 1024 512 = +VREFIN 1024 511 1024 1 1024
1000
0000
01(00)
(VREFIN)
1000
0000
01(00)
+2 (VREFIN)
1000
0000
00(00)
(VREFIN)
512 = +VREFIN/2 1024 511 1024 1 1024
1000
0000
00(00)
+2 (VREFIN)
0111
1111
11(00)
(VREFIN)
0111
1111
11(00)
+2 (VREFIN)
0000 0000
0000 0000
01(00) 00(00)
(VREFIN)
0000 0000
0000 0000
01(00) 00(00)
+2 (VREFIN)
OV
OV
* Write 10-bit data words with two sub-LSB 0s because the DAC input latch is 12 bits wide.
* Write 10-bit data words with two sub-LSB 0s because the DAC input latch is 12 bits wide.
Bipolar Configuration
A -VREFIN to +VREFIN bipolar range is set up by connecting ROFS to REFIN and RFB to VOUT, and operating from dual (5V) supplies (Figure 11). Table 5 shows the DAC-latch contents (input) vs. VOUT (output). In this range, 1LSB = VREFIN (2 -9).
Table 5. Bipolar (Offset Binary) Code Table (-VREFIN to +VREFIN Output)
INPUT* 1111 1111 11(00) OUTPUT (+VREFIN) 511 512 1 512
Four-Quadrant Multiplication
The MAX503 can be used as a four-quadrant multiplier by connecting ROFS to REFIN and RFB to VOUT, and using (1) an offset binary digital code, (2) bipolar power supplies, and (3) a bipolar analog input at REFIN within the range VSS + 2V to VDD - 2V, as shown in Figure 12. In general, a 10-bit DAC's output is D(VREFIN )(G), where "G" is the gain (1 or 2) and "D" is the binary representation of the digital input divided by 210 or 1,024. This formula is precise for unipolar operation. However, for bipolar, offset binary operation, the MSB is really a polarity bit. No resolution is lost because the number of steps is the same. The output voltage, however, has been shifted from a range of, for example, 0V to 4.096V (G = 2) to a range of -2.048V to +2.048V. Keep in mind that when using the DAC as a four-quadrant multiplier, the scale is skewed. The negative full scale is -V REFIN , while the positive full scale is +VREFIN - 1LSB.
14
1000 1000 0111
0000 0000 1111
01(00) 00(00) 11(00)
(+VREFIN)
0V (-VREFIN) 1 512 511 512 512 = -VREFIN 512
0000
0000
01(00)
(-VREFIN)
0000
0000
00(00)
(-VREFIN)
* Write 10-bit data words with two sub-LSB 0s because the DAC input latch is 12 bits wide.
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5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
+5V +5V
REFIN REFOUT 33F ROFS REFGND
VDD
REFIN ROFS
REFIN
MAX503
AGND DGND REFGND
RFB
AGND DGND
MAX503
RFB
VOUT
VOUT
VOUT
VOUT
VSS -5V -5V
Figure 11. Bipolar Configuration (-2.048V to +2.048V Output)
Figure 12. Four-Quadrant Multiplying Circuit
__________Applications Information
Single-Supply Linearity
As with any amplifier, the MAX503's output op amp offset can be positive or negative. When the offset is positive, it is easily accounted for. However, when the offset is negative, the output cannot follow linearly when there is no negative supply. In that case, the amplifier output (VOUT) remains at ground until the DAC voltage is sufficient to overcome the offset and the output becomes positive. The resulting transfer function is shown in Figure 13. Normally, linearity is measured after allowing for zero error and gain error. Since, in single-supply operation, the actual value of a negative offset is unknown, it cannot be accounted for during test. In the MAX503, linearity and gain error are measured from code 3 to code 1023 (see Note 2 under Electrical Characteristics). The output amplifier offset does not affect monotonicity, and these DACs are guaranteed monotonic starting with code zero. In dual-supply operation, linearity and gain error are measured from code 0 to 1023.
ground connection may be achieved by connecting the AGND, REFGND, and DGND pins together and connecting that point to the system analog ground plane. If DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass V DD (and V SS in dual-supply mode) with a 0.1F ceramic capacitor connected between VDD and AGND (and between V SS and AGND). Mount the capacitors with short leads close to the device.
AC Considerations
Digital Feedthrough High-speed data at any of the digital input pins may couple through the DAC package and cause internal stray capacitance to appear as noise at the DAC output, even though LDAC and CS are held high (see Typical Operating Characteristics). This digital feedthrough is tested by holding LDAC and CS high and toggling the data inputs from all 1s to all 0s. Analog Feedthrough Because of internal stray capacitance, higher-frequency analog input signals at REFIN may couple to the output, even when the input digital code is all 0s, as shown in the Typical Operating Characteristics graph Analog Feedthrough vs. Frequency. It is tested by setting CLR to low (which sets the DAC latches to all 0s) and sweeping REFIN.
Power-Supply Bypassing and Ground Management
Best system performance is obtained with printed circuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommended. The two ground planes should be connected together at the low-impedance power-supply source. AGND and REFGND should be connected together, and then to DGND at the chip. For single-supply applications, connect VSS to AGND at the chip. The best
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15
5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC MAX503
5 POSITIVE OFFSET 4 OUTPUT (LSBs) 3 2 1 0 1 2 3 4 5 NEGATIVE OFFSET
DAC CODE (LSBs)
Figure 13. Single-Supply DAC Transfer Function
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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